1. Field of the Invention
The present invention relates to a CCD shift register which may be applied to CCD solid-state imaging devices or other similar devices.
2. Description of the Prior Art
FIG. 1 shows one example of frame interline (FIT) type CCD solid-state imaging devices. In the figure, reference numeral 1 denotes an imaging section, 2 denotes a storage section, and 3 denotes an output section, that is, a horizontal shift register section having a CCD structure. The imaging section 1 has a multiplicity of light-receiving elements 4 arranged in a matrix to form pixels, and vertical shift registers 5 having a CCD structure, each disposed at one side of a vertical line of the light-receiving elements 4 to transfer signal charges from the light-receiving elements 4 to the storage section 2 in the vertical direction. The storage section 2 is disposed at the lower side of the imaging section 1, as viewed in the vertical direction, for temporary storage of signal charges generated in the imaging section 1. The storage section 2 has a plurality of vertical shift registers 6 similarly having a CCD structure which are disposed in one-to-one correspondence to the vertical shift registers 5 in the imaging section 1. Both the vertical shift registers 5 and 6 in the imaging and storage sections 1 and 2 employ a four-phase driving system, for example, in which the shift registers 5 and 6 are controlled with four-phase driving pulses .phi.IM.sub.1, .phi.IM.sub.2, .phi.IM.sub.3 and .phi.IM.sub.4 and .phi.ST.sub.1, .phi.ST.sub.2, .phi.ST.sub.3 and .phi.ST.sub.4, respectively. The horizontal shift register section 3, serving as an output section, employs a two-phase driving system, for example, in which it is controlled with two-phase driving pulses .phi.H.sub.1 and .phi.H.sub.2.
In solid-state imaging devices for high-definition (high-resolution) imaging applications, the horizontal shift register section 3 has a multichannel horizontal shift register structure in which two horizontal shift registers 3A and 3B, for example, are provided in parallel, as shown in FIGS. 1 and 2, in order to lower the horizontal transfer frequency. In this horizontal shift register section 3, a pair of first and second horizontal shift registers 3A and 3B are disposed with a transfer gate section 7 interposed therebetween, as shown in FIG. 2. A plurality of transfer electrodes 9, each comprising a storage gate electrode 9S and a transfer gate electrode 9T, are formed in common to the horizontal shift registers 3A and 3B. The driving pulse .phi.H.sub.1 is applied to a first group of alternate transfer electrodes 9, and the driving pulse .phi.H.sub.2 is applied to a second group of remaining alternate transfer electrodes 9. Hatched regions 10 are channel stop regions.
In this FIT type solid-state imaging device, fast sweep-away transfer is carried out during the vertical blanking period to sweep away the smear component from the vertical shift registers 5 and 6 in the imaging and storage sections 1 and 2 to a smear drain region 12 through a smear gate section 11. Thereafter, the signal charges in the light-receiving elements 4 are transferred from the imaging section 1 to the storage section 2 where the charges are stored temporarily. Then, for each horizontal blanking period, the storage section 2 distributes signal charges for one horizontal line to the first and second horizontal shift registers 3A and 3B in the horizontal shift register section 3. For example, signal charges e.sub.1 in alternate vertical shift registers 6 are transferred to the first horizontal shift register 3A, while signal charges e.sub.2 in the remaining alternate vertical shift registers 6 are transferred to the second horizontal shift register 3B. The signal charges e.sub.1 and e.sub.2 for one horizontal line transferred to the first and second horizontal shift registers 3A and 3B are transferred therethrough horizontally and then sequentially output alternately through switching means (not shown).
Conventional two-phase CCD shift registers which are applicable to the above-described horizontal shift registers 3A and 3B are shown in FIGS. 3 and 4.
A two-phase CCD shift register 14 shown at A in FIG. 3 has a semiconductor substrate 15 of a first conductivity type, e.g., p-type, a gate insulator 16 formed on one surface of the semiconductor substrate 15, a plurality of transfer electrodes 17 arranged in one direction, each transfer electrode 17 comprising a storage gate electrode 17S formed from a first-level polycrystalline silicon layer and a transfer gate electrode 17T formed from a second-level polycrystalline silicon layer, and p-type impurity regions 18 formed only under the transfer gate electrodes 17T with a higher impurity concentration than that of the substrate 15, thereby forming transfer sections, i.e., a first storage section st.sub.1, a second transfer section tr.sub.1, a second storage section st.sub.2 and a second transfer section tr.sub.2. The first storage and transfer gate electrodes 17S and 17T are connected to a bus line to which a driving pulse .phi..sub.1 is applied, and the second storage and transfer gate electrodes 17S and 17T are connected to a bus line to which a driving pulse .phi..sub.2 is applied.
In the two-phase CCD shift register 14, when charge transfer is to be effected, e.g., when the pulse .phi..sub.1 is at the high level, while the pulse .phi..sub.2 is at the low level, a staircase surface potential profile 20 such as that shown at B in FIG. 3 is formed owing to a potential difference based on the impurity concentration difference between the storage sections st.sub.1 and st.sub.2 on the one hand and the transfer sections tr.sub.1 and tr.sub.2 on the other, so that electric charge e is transferred in the direction of the arrow a. In this arrangement, a region A corresponding to the storage section st.sub.1 is a region which is capable of storing the signal charge e, as shown at B in FIG. 3.
A two-phase CCD shift register 21 shown at A in FIG. 4 is arranged so as to increase the transfer efficiency and the driving frequency. In this prior art, the p-type impurity regions corresponding to the transfer sections tr.sub.1 and tr.sub.2 are each divided into two subregions by varying the impurity concentration. More specifically, a first p-type impurity region 22 of relatively low impurity concentration and a second p-type impurity region 23 of relatively high impurity concentration are formed under each transfer gate electrode 17T, and the gate length l.sub.2 of the storage sections st.sub.1 and st.sub.2 is made shorter than the gate length l.sub.1 of those shown at A in FIG. 3, thereby allowing the transfer electric field to be readily applied. The other arrangements are the same as those shown in FIG. 3. Accordingly, a three-step potential profile is formed under each transfer section, as shown by a staircase surface potential profile 24 at B in FIG. 4, thus increasing the transfer efficiency and the driving frequency.
With the arrangement shown in FIG. 4, since the charge storing capacity of the region B decreases owing to the impurities, the region A mainly serves as a region capable of storing the electric charge e. More specifically, gate electrodes 26 and 27 are usually isolated from each other by an insulator 28, as shown at A in FIG. 5, and hence the insulator 28 is locally thick. When the driving pulses .phi..sub.1 =.phi..sub.2, the potential is modulated at the region between the gate electrodes 26 and 27, resulting in a potential barrier (or a potential dip) 29, which interferes with the charge transfer, as shown by a potential diagram at B in FIG. 5. Accordingly, it is necessary to establish either an electric potential difference between the gate electrodes 26 and 27 or an impurity concentration difference between the respective regions under the gate electrodes 26 and 27 and hence a surface potential difference so that the potential barrier (or the potential dip) 29 is canceled (see the potential diagram shown at C in FIG. 5). It should be noted that the chain line 30 represents a state where the barrier 29 is not canceled because the potential difference is not adequately large, whereas the solid line 31 represents a state where the barrier 29 is satisfactorily canceled with an adequate potential difference.
For this reason, the two-phase CCD shift register 21 shown in FIG. 4 necessitates raising the impurity concentration in each p-type impurity region 22 to thereby increase the potential difference between the regions A and B in order to cancel the potential barrier (or the potential dip) in addition to the purpose of obtaining a necessary transfer electride field (in this case the potential difference between the regions B and C decreases conversely). Accordingly, the region A mainly serves as a region capable of storing electric charge, as has been described above, and the amount of electric charge that can be handled decreases by an amount corresponding to the reduction in the gate length l.sub.2 in comparison to the arrangement shown in FIG. 3. In general, however, the decrease in the amount of electric charge can be compensated for by increasing the gate width of the CCD shift register.
In a case where the two-phase CCD shift register 21 shown in FIG. 4 is employed for the multichannel horizontal shift register section 3 of the solid-state imaging device shown in FIG. 1, if the gate width is increased in order to ensure the amount of electric charge that can be handled, the efficiency of charge transfer in the vertical direction (i.e., the direction V) from the first horizontal shift register 3A to the second horizontal shift register 3B lowers. An effective way of improving the vertical transfer efficiency is to shorten the vertical gate length (and hence the gate width of the horizontal shift register). As a consequence, the prior art suffers from the problems that if the two-phase CCD shift register 14 shown in FIG. 3 is employed for the multichannel horizontal shift register section 3, the horizontal transfer efficiency lowers, whereas, if the two-phase CCD shift register 21 shown in FIG. 4 is employed therefor, the amount of electric charge that can be handled decreases.